The exemplary implementations of the subject matter described herein relate to a delay-locked loop circuit and a semiconductor memory device including the same, and more particularly, to a delay-locked loop circuit capable of decreasing power consumption and a locking time and a semiconductor memory device including the same.
In systems or circuits, a clock signal has been used as a reference signal for synchronizing timings of operations and used to guarantee more rapid operations without causing errors. When an external clock signal supplied from the outside is used inside a system, clock skew may occur due to an inner circuit. A delay-locked loop circuit is used to compensate for the clock skew so that an internal clock signal of a semiconductor memory device may have the same phase as the external clock signal.
Recently, semiconductor memory devices have been developed to perform operations at higher speeds and thus high-frequency clock signals have been more frequently used. As high-frequency clock signals have been used, the amount of electric power to be used to generate an internal clock signal having the same phase as an external clock signal has increased and may thus prevent a low-power consuming semiconductor memory device from being realized.